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PXIe-4304 causing ripple on input signal?

April 11, 2016, 11:43 am
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I have a PXIe-1082 chassis that contains a PXIe-6341 and a PXI-4304 module.  To check my code, I've connected the analog input (channel 0) of the 4304 to the Digital output (PFI 12) of the 6341.  My VI program is showing a 0.2 Vpp ripple on the analog input that I'm not seeing using a scope. 

 

The wiring is PXIe-6341 [PFI 12, DGND] -> SCB-68A --> TB-4304 [AI0 +,-] -> PXIe-4304

 

I've attached pictures of the scope verses the VI graph.  The scope is measuring at the AI0+ and AI0- terminals on the TB-4304.
 

Is there an extra ground that I should be using, or is it normal for the -4304 to add ripple?

 

Thanks,

Ron

 

 

 

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lost data from PXIe on Veristant

April 12, 2016, 2:26 am
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Hello,

 

i am running a model on Versitand and am trying to find the max frequency at which i can run it.

 

i am using the configuration benchmarking tool to find the model limits. also is there any elaboration of what the configuration benchmarking tool dose. i assume it changes the PCL value periodically and sees if the model runs successfully?. 

 

i am noticing that on the workspace simple graph within veristand that the graph periodically has a blank period i.e lost data even when i set the pxie to run at the max loop max that the benchmarking tool specifies. i would have thought that the max freq from the configuration benchmarking tool would be sufficent for the model?

 

is the data presented on the workspace graph the real time data that the pxie is calculating? i am wondering is there not a limit set by the bandwith of the TCP/IP connection? i am comparing the pxie model to that of the simualted model and would expect to see the same shape i.e. steps as this is discrete.

 

thanks

 

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Trouble using two scb-68a on NI PXI 6225

April 13, 2016, 10:12 am
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Dear Ni Forum,

I have a NI PXIe-1078 chassis, with NI-PXIe8135 embended controller. One of the slot is occupied with a PXI-6225. I have been succesfully using 1 SCB-68A connector block with the PXI-6225. Now, I am in need of another analog output channel on top of the two AO that I am current using. I connected another SCB-68A connector board to the PXI6225 but I have been unable to see analog output channels on this second board. I have been unable to see more AO channels through DAQmx Create Channel VI 

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4138 analog out

April 14, 2016, 2:39 am
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Hey,

in the summary spec of the 4138 we find: analog out: max 10mA singing 3A.

In the detail spec we find: 330mA out at 10V.

 

which one is right?

 

thx

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PXIe-6704 Measuring Analog Output Signal

April 14, 2016, 7:52 am
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hello

 

i have a PXIe with an analog output card 6704.

 

i am emulating a signal and have mapped it to the 6704 analog output. i have connected an SCB-68A breakout box this card and and am trying to view the signal on an oscilloscope.

 

the emulated signal is running at around 35kHz and the signal is a sinewave at around 400Hz.

 

i have connected the oscilloscope to terminal 22 and the gnd to terminal 55 on the SCB-68A but and not seeing the wave.

 

i am wondering if the card is suitable for presenting an emulated signal such as this in the for of a 0..10V analog signal?

 

thanks

Brendan

 

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How to connect PXIe 1075 with system controller to external PC

April 18, 2016, 7:32 am
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Hello All,

 

Can anyone let me know is that possible to connect and configure PXIe 1075 with system controller to external PC with Windows7.

 

Thanks

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PXI 6040E: How to generate a counter from an analog sine with varying frequency and synchronize this counter with the analog sine?

April 19, 2016, 2:54 am
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Hi,

 

I am currently using the PXI-6040E board to collect an analog sinewave from an analog signal generator. The frequency of this analog signal is slightly varying (100 Hz variation to 40000 Hz base). I am trying to generate a counter which runs synhronized with this analog signal at a rate of 240 kHz (=6*40kHz). With this counter I later want to sample my incoming measurements which I collect on the PXI-6123 board. 

I am using the CounterPulse.vi which I found here.

The two images in attachment show how I am trying to accomplish this. Yet when I try to run it I get following error: 

 

Error -200557 occurred at Property Node DAQmx Channel (arg 1) in Pulse Generation from Analog.vi

Specified property cannot be set while the task is running.

Set the property prior to starting the task, or stop the task prior to setting the property.

Property: CO.Pulse.Freq

Task Name: _unnamedTask<80>

 

Can anyone help me with this problem? 

 

Thank you very much in advance!

 

Dieter

 

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FlexRIO maximum input data rate

April 21, 2016, 3:54 am
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Hello.

 

I'm using a 7966R/6581 FlexRIO system, and want to use the same to perform some IO operations. 

 

The datasheet (linked here to the relevant page) of the FPGA module says that the maximum data rate is 400 Mb/s for single-ended LVDCI25 operation. I tried searching for what that it is, but I don't seem to be able to find a comprehensive definition for it. I'm planning on sending signals of 3.3 V to the FPGA. I've previously done so with lower speeds (of the order of a few 100 kHz), but I need to push up to about a few MHz now, and I want to ascertain how much error there can be with edge-related timing measurements, if I've to make them.

 

Please help me understand what exactly LVDCI25 is. I'll be coding using LabVIEW FPGA, are there any adjustments of any sort I might have to make?

 

Thanks!

 

 

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cross chassis pxi triggering of FlexRio with NI-Sync

April 21, 2016, 11:09 am
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I am sending a trigger pulse to cards in two chassis:

1) PXI-1042Q with PXI-6653 (sync card "Sync") and PXI-6133 and PXI-6602

2) PXIe-1082 with PXIe-6672 (sync card "Sync1") and PXIe-6962 FlexRios.

I developed the setup based on a previous NI forum post, where you can also see my NI-Max setup (Sync0 has been renamed Sync1): http://forums.ni.com/t5/PXI/trigger-multi-chassis/m-p/3169983/highlight/true#M15036

 

I have connected PFI 0 of Sync to PFI1 of Sync and PFI2 of Sync to PFI0 of Sync1 with coax cables. With NI-sync I connect PFI0 and PFI2 of Sync to a global software trigger and then PF1 of Sync to the PXI_star lines of each of the cards in the PXI chassis and the PFI0 of Sync1 to each PXI_star line of the FlexRios in the PXIe chassis. 

 

sync.PNG

 

In the FPGA code, after initializing the FPGA and the FPGA adapter I have a 50MHz timed loop look at the PXI_Star line. The PXI_Star line triggers a counter, once the counter reaches a threshold a stream vi is triggered which controls my data acquisition. However, I found that the timing on the PXIe chassis seems to differ greatly from the PXI chassis. Also if I replace the PXI-Star line with PXI_trig in the FPGA code the triggering still occurs. It does not occur if I hardcode a "False" instead of the PXI_Star line. I think  for some reason there is a pulse on the PXI Star lines before the NI-Sync initiated trigger. Does anyone have an idea what is going on?  

 

rio_trig.PNG

 

I am sorry that I currently only have screen shots. I am working on separating a small self-contained test case form the larger code. 

 

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AI big difference in ranges / multi-channel ancquisition

April 23, 2016, 2:21 pm
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Hello,

 

I am stuggling to get my system to work well. I am using analog inputs at NI PXI-6363 card, I measure 16 AI differentially.

 

AI0 is set to -0.1 V to 0.1 V range, I need about 0.1mV precision on this channel (it is 100mV output pressure transducer)

others are set to 0 to 10 V range, I measure voltages in this range.

 

When I configure task on all channels I end up with interferences between channels. I read 2.3V on AI6 and just after that I measure 5mV on AI0 whereas real signal on AI0 is -0.5mV. This happens on acquisition rate 100Hz, and AI convert rate 90kHz (default value).

To eliminate this intererence I tried to decrease AI convert rate (using timing property), but I had to go all way to the 2kHz. Then it was ok, whereas still not that stable as if I would measure only AI0. I can never get that stable data, even if I decreased AI convert rate to 60Hz.

 

I need data with defined specific time (100Hz sampling and be able to increase it).

I know it is an interference from previous channel because next channel voltage reacts on change of previous channel voltage.

Issue occures when I acquire these channels one after another. 

 

Do you please have any idea how to fix this problem?

Is there a way to put time gap between AI conversions? (timestamp difference of  channels had always the same value 11us no matter of AI convert rate property setting).

 

Thank you for your ideas and answers.

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8880 Dequeue Element blocking

April 25, 2016, 3:31 am
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I've got a large PXI program that operatures fine on a PXI 8106 and a PXIe8135. However, running the exact same code on a PXI 8880 freezes after a while (often within a few hours, sometime a few days).

 

We've narrowed it down with logging to the Deqeue Element primative. It has a zero time out, but blocks any code further on from executing. We're running the lastest 2015SP1 and drivers, but still seeing the same issues.

 

Has anyone seen anything like this before?

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Strobe placement within clock period

April 25, 2016, 6:48 am
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Hello, all.

 

I'm using the 7966/6581 FlexRIO system to perform timing characteristic measurements for the I2S protocol. 

 

I was wondering whether there is a way to control the strobing point within a particular period of a signal for measurements with respect to another signal.

 

What I mean to say is, I'm sending a bit clock and serial data from the FPGA that is clocked on this bit clock. Is there a way for me to read back this data with respect to this particular clock and a certain controllable offset? If yes, what is the resolution that this operation can be performed to?

 

Currently, I'm using an SCTL that is run at a much higher frequency than the bit clock, and the data is reviewed for a write once every tick. The read-back code hasn't been written yet. However, I ideally need to go to about a GHz for the clock of the SCTL if I am to perform setup/hold time measurements using this method. So, if the above operation cannot be performed, can I run the SCTL at that speed, considering that the FPGA module datasheet mentions the maximum I/O data rate to be 400 Mbps (single-ended), or does violating this not come into the question if I'm not going to be writing (or reading) values at that rate?

 

Moreover, is 400 Mbps the double data rate, or does this assume that data is being clocked only on one edge?

 

Thank you very much!

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PXI rack devices seen but not working

April 27, 2016, 1:54 pm
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I have two PXI racks and two test PCs.

One set up is my development system and the other is a test sytem that is at a remote location.

 

Recently, I was experieincing problems with the remote PC and I brought it to my site and connected it

to my PXI rack. At that time, the PC would see all the PXI devices in NI-Max but would not measure when

accessed by its test stand seq file but the test panels worked OK.

 

Not sure what i did but it started to work and I set the PC back to the remote site. The site is now reporting

that the PC sees all the devices in its original rack but will not measure from the teststand seq. file that was set

up and running before.

 

 

PXIe NI-Max config.jpg

 

I am planning a trip to this remote site and am looking for suggestions of what to try.

 

Any timely helpful suggestions are gfreatly appreciated...

 

Thanks

 

 

 

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Inconsistent IP setting error. PXIe-8135

April 29, 2016, 11:17 am
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Hello NI Forum,

I recently got a new laptop. I want it to work with NI PXIe-1078 Chassis with PXIe-8135 Embeded Controller. I am having a problem connecting to it. There is an error at Measurement & Automation Explorer >> Remote Systems >> NI-PXIe8135-####### >> Status "Inconsistent IP Settings".

 

I tried this http://digital.ni.com/public.nsf/allkb/A0F6EFF8A33578948625749C006DEC3B but it would not let me change to static IP. Please help.

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No Option to set up PXIe-1078 as target in Labview Project

April 29, 2016, 3:24 pm
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Hello NI Forum,

 

I am relatively new to real time programming in LabView.  I have a PXIe-1078 which I would like to use for a DNET application.  I see that the Chassis and the card are functional and showing up in NI Max, but I am unsure of how to reference the PXIe-1078 within a LabView Project.  I have tried to find tutorials to meet this end but have been unable to find anything.  If anyone can give a some information and or tutorials on how to set up the PXIe-1078 within a LabView Project, I would greatly appreciate it.  Thank you for your time.

 

 

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Continous simultaneous vibration and voltage acqusition using PXI

May 2, 2016, 3:13 am
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Hi everybody!

 

First of all thank you for your help in advance!

 

I am pretty new using PXI systems. Previously I used Labview for simple DAQ applications only. Now I am in a great time pressure to solve a DAQ problem using PXI. Your comments and inputs are greatly appreciated.

 

For an academic project we need to continuously acquire and log acceleration signals from 6 channels and voltage signals from 7 channels simultaneously at 22050 Hz sampling rate each. We have a remotely controlled PXI-1031 chassis with PXI-6221 DAQ card which I connected the voltage cables and PXI 4472B which I connected the acceleration cables. I collect the signals using the attached VI for around 15-20 sec for each experiment I conduct.

 

When I opened the collected signals with Diadem afterwards I realized that there are data losses for some channels. When I searched the forum and internet for answers I came up with 2 main ideas: Data queing and low level VIs but I am not sure. So my questions are:

 

- Is there a basic step that I miss which would solve my problem without applying queing or low level VIs?

 

- Can I solve this data loss problem with queing and low level VIs or is there something else that I should do?

 

- Do you know any additional documentation or link to solve such a problem?

 

I know I miss some fundemental knowledge and am constantly trying to improve myself buts ince I have a great time pressure I thought posting here and getting some answers would speed up the process. So thank you for your patience as well !!

 

Cheers,

Bircan

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PXI-5105 Digitizer

May 2, 2016, 10:42 am
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Hi,

I send same question on last friday.

The digitizer we are using has a  error occurred.

we are using wondows 8 computer, running Max program.

The Error code is 200313 occurred at Self-Test.

 

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6682 IEEE 1588 Implementation

May 3, 2016, 8:05 am
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Hello,

 

We presently have an extensive PTP network setup to synchronize our PXI chassis and recently looked into adding a 1588 slave from another vendor onto this network.  However, it appears that the 1588 implemented in the 6682 and 6683 are based upon UDP, which is allowable in version 2.  However, our other vendor uses a lower level implementation on the data link layer, not the transport layer.  We have presently setup our 1588 network with the 6682s by simply using MAX and the test panels and do not have any code on the RT chassis that actually sets this up but we aren't opposed to it if needed.

 

Does anyone have any experience or recommendations in possible solutions to this?  I figured we would ask before we tried to go down what might be a very dark tunnel.

 

Thanks,

 

Curtiss

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Fuse for PXIe-2531

May 3, 2016, 1:49 pm
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Hi,

 

I have a PXIe-2531 that is not working at all.  I quickly took a look at the fuses on the board and discovered one of them is bad.  I have the tools and ability to replace the fuse i just need to know what to replace it with.  

 

Thanks. 

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7953 FPGA with 6583

May 4, 2016, 11:08 am
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Hi,

Have a PXIe-1078 with 7953 FPGA & 6583 .

it is a new setup so I am comparing test setups.

I have no clk output.  I've never had this problem before.

I've rechecked everything so reaching out as to what the possible

sources of this problem might be.   On teh other station I see 50 Mhz on the scope.

Any hints.

Thanks,

Patrick

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