Hello，
I want to use one 6674T to Generate two clock, 10kHz and 120MHz. The clocks should phase locked to PXI_CLK10_IN.
Acording to the manual, I think I can Generate one clock with its phase locked to PXI_CLK10_IN.
The clock generation circuitry is based on a direct digital synthesis (DDS with an 800 MHz reference phase locked to PXIe_CLK100.
Most PXI Express backplane architectures employ a PLL to lock a 100 MHz reference oscillator to the signal coming from the PXI_CLK10_IN pin. This 100 MHz reference is then used to directly create PXIe_CLK100 and is divided down by ten to create PXI_CLK10.
Thanks.
Henry