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RFSA p2p dynamically change carrier frequency

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Hello,

We have puchased PXIe-5665 and PXIe-7975R. IQ samples are transferred to FlexRIO with p2p and then transferred to host code. I realized that I cannot change the carrier frequency after I initiated RFSA once. I tried stopping RFSA, disabling p2p session and re-enabling it. All of these gave different errors.

 

Could you please share an example that changes the carrier frequency dynamically without closing RFSA and p2p sessions.

 

Thanks,

Ozan


RFSG Synchronization TClk

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Hi.

 

I try to synchonize two PXI-5651 but I have an error:

Error.png

Please tell me where I have an error? Thanks.

 VI.png

 

Can't add MXI Chassis connected to RT PXI to a LV Project

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I have an MXI chassis connected to an RT PXI.  On the host machine, I can see both the RT PXI and the MXI chassis and can access the MXI FPGA to flash a bitfile, etc.

 

But in my LV project, I cannot add the MXI FPGA target.  I can only add the RT PXI but attempting to add the MXI target under the PXI yield no FPGA device found.

How to shut down the NI PXIe-1073 chassis?

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Hi community,

I just started using NI PXIe-1073 chassis.I was wondering how to power off the chassis manually when required. There is a way to shut the chassis down when it gets stuck by keep pressing the front power button for 3 seconds. Is there any other way to power down the chassis? Thank you!

Best regards,
Ahmad

Simulated PXIe-4535 bad sample results

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1. Define a Simulated Device - PXIe-4535 in MAX.

2. Open "Test Panel"

3. Use the default parameters of the test:

  a. Measurement type - thermocouple

  b. Max Input Limit - 100

  c. Min Input Limit - 0

  d. Units - Deg C

  e. Thermocouple type - J

  f. CJC Source - Built In

4. Click Start.

 

The result is Sin Wave.

The sample values range ~[-1030,-74.7], out of the Max/Min Limits.

=> BAD sample results, values lower than -273 C ?!?!?!?!

 

If I change the Max/Min Limits to other valid range like [-200,1200]

The sample values range is BAD

And, the result is some kind of Non-Sin Wave

 

If I change the Measurement type to Voltage.

The sample values range is based on the Max/Min Limits.

=> So it is OK

 

P.S.

I check with other Simulated Device - PXIe-4303.

The sample values range is based on the Max/Min Limits.

=> So it is OK

  

PCIe-8371 is in then PC monitor is dark

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Hello Guys, 

 

We just changed a new PC, and when we insert the PCIe-8371 card in PCIe X16 port then restart the PC, we find that the monitor does not show anything. Do you have any ideas how to solve this problem? 

 

Thanks

PXIe-8840 problem with PXIe-4463 and PXIe-4492, error code 200757

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I'm using a PXIe 8840-Card in a 1062Q-Chassis, with two board card PXIe 4463 and one board card PXIe 4492. I plan to use Veristand collaborative with simulink to process a simulation. I set system RT at 5000hz, so the board sample rate could consistent with system RT. But, I got error code - 200757 to deploy with “device input does not support the sample rate defined “.

 

So I did a trouble shoot to test one another card, the simulation works well with PXIe-6368. I could find what`s issue of the error - 200757.

 

The following is my debug: 

 

ï Start Date: 2018/7/4 16:46

ï Loading System Definition file: D:\NI\mod\mod\mod.nivssdf

ï Initializing TCP subsystem...

ï Starting TCP Loops...

ï Connection established with target Controller.

ï Preparing to synchronize with targets...

ï Querying the active System Definition file from the targets...

ï Stopping TCP loops.

Waiting for TCP loops to shut down...

ï TCP loops shut down successfully.

ï Unloading System Definition file...

ï Connection with target Controller has been lost.

ï Start Date: 2018/7/4 16:46

ï Loading System Definition file: D:\NI\mod\mod\mod.nivssdf

ï Preparing to deploy the System Definition to the targets...

ï Compiling the System Definition file...

ï Initializing TCP subsystem...

ï Starting TCP Loops...

ï Connection established with target Controller.

ï Sending reset command to all targets...

ï Preparing to deploy files to the targets...

ï Starting download for target Controller...

ï Opening WebDAV session to IP 192.168.68.21...

ï Processing Action on Deploy VIs...

ï Gathering target dependency files...

ï Downloading mod_Controller.nivsdat [232 kB] (file 1 of 3)

ï Downloading CalibrationData.nivscal [0 kB] (file 2 of 3)

ï Downloading mod_Controller.nivsparam [0 kB] (file 3 of 3)

ï Closing WebDAV session...

ï Files successfully deployed to the targets.

ï Starting deployment group 1...

* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *

The VeriStand Gateway encountered an error while deploying the System Definition file.

 

Details:

Error -200757 occurred at Project Window.lvlibSmiley Tongueroject Window.vi >> Project Window.lvlib:Command Loop.vi >> NI_VS Workspace ExecutionAPI.lvlib:NI VeriStand - Connect to System.vi

Direct access to PXIe trigger bus

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I am thinking about building an RF supply system around a Keysight M3202A AWG housed in a PXIe chassis.  The AWG has an option to use an integrated FPGA to perform realtime feedback, but the problem is that the AWG only accepts digital inputs (besides the trigger) through the backplane. 

 

Since I would like to pipe in as many digital signals as possible, is there any way to access the PXI trigger bus directly?  The timing and synchronization modules (PXI-6683, PXIe-6672, and PXIe-6674T) only give access to 3 or 6 trigger lines through PFI lines.  They also include onboard high-accuracy clocks that I do not need; in fact, I will select a chassis with an external clock input precisely because I need to sync it to our master experiment clock.  Something as simple as 8 SMB inputs on the front panel connected to the bare minimum of routing circuitry would be perfect, but it's not obvious that such a card exists.

 

Also, I'm assuming that, even though the trigger bus is designed to transmit short trigger pulses, the lines can also handle being driven high or low for long periods of time to serve as flags.  Please correct me if I'm wrong on this.

 

Thank you for your help!


PXIe-8375 not seen on Windows 10

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Hello, I had a PC with Windows 7 pro and a PCIe-8375 on it, and a PXIe-8375 on a PXIe 1085 rack with a fiber optic cable between them, and all the cards Inside the rack was well seen by NI-Max.

I've upgrade this PC with Windows 10 pro, but now only the PCIe-8375 is seen by NI-Max.

I've tried to use the "NI MXI-Express BIOS Compatibility software", as suggested in NI Forum, but this software doesn't work on this PC (probably because it had a multi root PCI bus).

What can i do to resolve this issue ?

Thanks,

DAQ-mx read unexpected time-out error instead of sample clock late error

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Hello,

I'm using PXIe-4340 4 Ch AC LVDT to measure a quantile of a valve.

So we are using the DAQ-mx Read VI with Hardware timed single point for the sample clock as the attached picture.

The sampling freq. is 10KHz. The vi is "time critical priority" in order not to be influenced from other vi running.

Somehow we will have the error "-200474" relating to timeout not operated in the specific time.  

This error looks like that the sample clock can't make in the hardware-timed single point for some reason.

The error occurs once the vi runs after around 10 hours. It should be stable running because the RT CPU load is around 30 to 40%.

We don't think  the timeout error occurs by the affection of the default time out setting 10sec of the DAQ-mx read vi even if the hard-ware timed single point gets unstable once in the sample clock. We think it can make it in the timeout setting.

And we think the error should be something else relating to "sample clock late" Not like the timeout error in this case. 

Once we get the timeout error, we can't have next measurement cycle, the vi waits forcibly until the specified timeout settimg time comes out. 

 Does anyone  know  what kind of error is expected to come out in the case? timeout or sample clock late?

Vos on NI-6561

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Is there a way in software to changed the level of Vos on the NI-6561 LVDS card?

OPC Help

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I want to be able to have a NI-PXIe 8135 talk to the NI OPC server so I can in turn have GEs iFIX talk to the NI OPC server and us it as the HMI. 

 

PXIe-8135 <->NI OPC Server <->iFIX


I am running Labview 2017. I bought the HIL and Real-Time Test Software Suite ( http://sine.ni.com/nips/cds/view/p/lang/en/nid/212458) and the NI OPC server ( http://sine.ni.com/nips/cds/view/p/lang/en/nid/209059). 

According to http://zone.ni.com/reference/en-XX/help/370622P-01/lvmve/opcua_pal/, "You must activate the LabVIEW Real-Time Module to use the OPC UA VIs on a real-time target" 

I have the LabView Real-Time Module activated. 

Do I actually need the Labview OPC UA Toolkit (http://sine.ni.com/nips/cds/view/p/lang/en/nid/215329) for these VIs? They do not current show up in "C:\Program Files (x86)\National Instruments\LabVIEW 2017\examples\comm". Plus if I right click on the real-time target in Labview and select New -> I/O Server, I do not see OPC as an option (only EPICS).

Or is there a simpler way to connect to iFIX to get the data off of the PXIe?

niGPS

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I'm trying to streaming a waveform to an PXI-5671 based on example on niGPS Streaming from file (5671). Anyone know if it's possible do this type of operation in this equipment? I am getting some erros on property node ("Streaming waveform name") because  Attribute ID isn't recognized.

LFH200 cable terminal screw broke

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I am using a SH200LFH-4xDB50F-C cable for my relay PXI card, it works fine. But when I tightened down the one of the securing screws of one of the D-SUB connectors into the terminal block, the screw broke. Is there a way to order a replacement for just the little securing screw for this connector? See the attached image to see which securing screw I'm talking about.

Can a single VST generate more than 1 target using a mmWave head?

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Can a single VST, by itself, generate more than 1 target using a mmWave head?  Can it do so in conjunction with some other PXI module or do you actually need one VST for every generated target?


No PC / PXi communication via 8335 MXI-3 card

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When I start running the test bench application, the application starts but there is no communication between the PC (Dell Vostro 220 Mini Tower Desktop) and the PXI-1010 chassis (via 2 cards 8335 MXI-3). The green
LEDs PWR & LINK are lit while the orange LEDs RX & TX are off.
The material seems OK because:
- during the communication self-test during the application startup, the RX & TX LEDs as well as the orange LED on the PC flash
- and in DAQ in test mode of an input / output card (example PXI-6040E) the communication works continuously
-> this seems to be a problem of soft which nevertheless has not been modified but I do not see how to launch this communication.
Thank you in advance for your help. Have a good day.

Patrick

PXI-6541 Memory

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Running the following Matlab code:

Visa6541Address = 'PXI17::14::INSTR';

vv=visa('ni',Visa6541Address)
fopen(vv)

reg1 = memread(vv,0,'uint16','PXICFG',3)

fclose(vv)

 

Results in reg1 = 4243, 28887,6

Where is there a reference to tell me what these number mean please?

 

Converting PXI Peripheral card to PXI Hybrid?

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I have two PXI-4220 cards that I would like to use on a PXIe-1078. I assumed (incorrectly) that PXI hybrid meant that the slot would take it. Is there any kind of conversion riser or adapter that will allow me to use these cards with this chassis?

Custom PXI Chassis/Backplane wont show in MAX

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Hey,

I am trying to connect a custom build PXI Chassis/Backplane to a Windows 7/10 pc (PXIe 8360 / PCIe 8361).

 

Problem:
The Chassis wont show up in MAX, cards inserted in the chassis do just fine. It just shows the "NI SMBus Controller...:"

If i switch the resource manager to "Keysight Technology" (which i installed) the chassis shows up correctly with the cards underneath and the "NI SMBus Controller..." is gone again.

 

I am pretty sure I missing just a small part, but cant figure it out yet. Maybe someone stumbled over the same problem in the past and can give me a hint.

 

br

Michael

1.6 GB/s per-slot PXIe bandwidth

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We are trying to select a PXIe system to house an AWG we are going to evaluate.  The AWG (Keysight M3202A) will support 1.6 GB/s (4 lanes) bandwidth when used with a Gen 2 PCIe link and 400 MB/s (1 lane) when used with a Gen 1 link.  We would like to take full advantage of this bandwidth.  We will probably have a few other cards in the chassis as well, but nothing that will require appreciable bandwidth.

 

The PXIe/PCIe-8381 controller pairing seems best, as that will give us 8 lanes of Gen 2 bandwidth from the PC to the PXIe chassis.  My question mostly concerns the chassis itself.  The PXIe-1082 is most cost-effective; we need an external clock input, eliminating more basic models.  The problem is that it only supports 1 GB/s per-slot bandwidth.  Where is the bandwidth limitation?  From the 1082 manual, it seems that the controller slot has a direct x4 link to slot 2.  If we put the AWG in slot 2 and left all other slots empty, why could we not achieve the full bandwidth (1.6 GB/s) of a x4 Gen 2 link?  The PEX8612 switch seems to be a Gen 2 device, which seems to imply that the chassis lanes should support Gen 2 speeds.

 

Thank you for any help you can give.

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